Within a receiver of a wireless communication system, such as a code division multiple access (CDMA) system, many complex processing tasks are performed. An example of such a processing task is a fast hadamard transform (FHT), which may be performed by an integrated circuit or a digital signal processor. Due to power dissipation considerations and a limited number of available clock cycles, it is desirable to improve the performance of any FHT implementation by increasing the processing speed and reducing the amount of power consumed. In addition, in an application specific integrated circuit (ASIC), a premium is placed on the number of gates used. Thus, it is desirable to reduce the number of gates used by an integrated circuit device performing the FHT function.
Accordingly, there exists a need for a method and apparatus for FHT processing with increased speed, reduced power, and a reduced number of gates.